Senior Engineer/Staff

About Company

AMCC is a global leader in network and embedded Power Architecture processing, optical transport and storage solutions. Our products enable the development of converged IP-based networks offering high-speed secure data, high-definition video and high-quality voice for carrier, metropolitan, access and enterprise applications. AMCC provides networking equipment vendors with industry-leading network and communications processing, Ethernet, SONET, OTN and switch fabric solutions. AMCC’s 3ware SAS and SATA RAID product families deliver cost-effective, high-performance, high-capacity storage for enterprises and consumers worldwide for applications from the desktop to the data center. AMCC’s corporate headquarters are located in Sunnyvale, California. Sales and engineering offices are located throughout the world.

About AMCC India:

AMCC has commenced its India Design Center in Dec 2008 with a view to tap the ample talent in the VLSI domain and for embedded software development and QA. Based in Kalyaninagar, Pune, the state of the art facility would house multiple teams for SOC RTL design and verification, high speed board design, validation, embedded software development and QA of the same. In near future, it would be the largest development center outside of USA.

The high caliber team is expected to work on the various products of AMCC based on very top end architectures using PowerPC cores. Its leadership in 10 Gigabit Ethernet and other Storage technologies makes it a very exciting place to be.

Kapil @thehumancapital.net

Job Description

Position: SeniorEngineer/Staff Design Engineer (Transport)

Location: Bangalore/Pune

  • Candidate is expected to participate n all facets of front digital ASIC design: developing detailed design requirements, architecture design, VHDL or Verilog RTL detailed design, unit level simulation, follow DFT guidelines, generate test plans, STA, equivalence checking, conduct design reviews, etc.
  • Should be well versed with use industry standard tools such as Cadence RC, Synopsys PrimeTime, DC-Compiler, etc.  used to generate netlists for backend.
  • Knowledge of communications protocols an asset: OTN, Ethernet, Sonet, GFP, PON, Error Correction Codes, Flow control, Queuing architectures
  • Knowledge of relevant standards  (IEEE, ITU,etc) a plus.


  • Responsibilities will include block level ownership of design, unit level verification, design reviews.
  • Working in a team environment on multi overseas sites projects particularly with offices in the US/Canada


  • BSEE, MS (preferred)
  • Experience with multimillion gate design, COT, multi-clock, high frequency design with an emphasis on low power.
  • Must have good communication skills and the ability and desire to work as a team. Background in communications/networking a plus

Optional Experience:

  • Patents are a plus
  • Knowledge of place and route a plus
  • Knowledge/Experience of FPGA Design an asset
  • Experience with sub 65ns technologies an asset


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